{"id":4271,"date":"2026-01-14T17:17:15","date_gmt":"2026-01-14T15:17:15","guid":{"rendered":"https:\/\/catedrachip.upc.edu\/project\/implementing-a-65nm-rtl-to-gdsii-soc-design-flow\/"},"modified":"2026-05-27T11:04:24","modified_gmt":"2026-05-27T09:04:24","slug":"implementing-a-65nm-rtl-to-gdsii-soc-design-flow","status":"publish","type":"project","link":"https:\/\/catedrachip.upc.edu\/en\/project\/implementing-a-65nm-rtl-to-gdsii-soc-design-flow\/","title":{"rendered":"Goleta UPC: Implementation of a SoC RTL-to-GDSII design flow in 65nm"},"template":"","class_list":["post-4271","project","type-project","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/catedrachip.upc.edu\/en\/wp-json\/wp\/v2\/project\/4271","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/catedrachip.upc.edu\/en\/wp-json\/wp\/v2\/project"}],"about":[{"href":"https:\/\/catedrachip.upc.edu\/en\/wp-json\/wp\/v2\/types\/project"}],"wp:attachment":[{"href":"https:\/\/catedrachip.upc.edu\/en\/wp-json\/wp\/v2\/media?parent=4271"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}