High-speed serial data transmission circuit for image sensors

Description

The objective of this project is to design and implement a complete analog front-end for high-speed serial communications based on the emerging MIPI C-PHY protocol . The system incorporates a built-in self-test (BIST) architecture that allows validation and diagnostics on the chip itself, ensuring reliable performance evaluation after manufacturing . The MIPI C-PHY standard uses a three-level signaling scheme over three wires per lane, achieving higher data transmission rates while reducing electromagnetic interference (EMI) and improving signal integrity.

Background

Enrique obtained a degree in Telecommunications Engineering from the University of Cantabria (UC) in 2003. He subsequently obtained a doctorate with honors in Electronic Engineering from the Polytechnic University of Catalonia (UPC) in 2011. He currently works as an expert designer in CMOS technologies.

Motivation

His main motivation is to apply his doctoral experience in the design of high-speed data transmission circuits for advanced image sensors. He considers the implementation of the MIPI C-PHY protocol to be a key technical challenge to achieve competitive performance levels in the microelectronics sector. The project allows him to integrate innovative diagnostic solutions, such as the BIST architecture, to ensure the reliability of post-manufacturing devices.