Design of Chip-Level Digital Subsystems for a Hybrid-Stacked Image Sensor

Description

The goal of this project is to develop a hybrid stacked CMOS image sensor by vertically combining two dies. The upper die is dedicated to image capture, while the lower one is responsible for digital image processing. By separating these functions into a 3D stacked architecture, the design overcomes the limitations of planar sensors, allowing for better performance within a more compact package.

Background

Andreu completed his Degree in Industrial and Automatic Electronic Engineering at the University of the Balearic Islands (UIB). During this period, he completed a six-month Erasmus stay in Padua, Italy. After completing his degree, he worked for a year at Estel Ingeniería y Obras, a company in the facilities sector. Later, he started his Master's degree in Electronic Engineering at the Universitat Politècnica de Catalunya (UPC).

Motivation

Andreu chose this research project because of his strong motivation towards digital design. He believes that it will provide him with valuable experience and allow him to expand his knowledge. Furthermore, he believes that this field of research is particularly suitable for the development of his Master's Thesis.