Microcredential in Functional Design and Verification Based on the SystemVerilog Language

You can now apply for admission to the Microcredential in Functional Design and Verification Based on the SystemVerilog Language. This intensive training, which will be given at the UPC – Campus Nord in Barcelona from May 18 to 22, 2026 , offers a key specialization in one of the most promising areas within the semiconductor industry.

The course provides a solid foundation in digital design with Verilog and delves into advanced features of SystemVerilog, including structural and behavioral description, synthesis, advanced data types, and interfaces. It also introduces object-oriented programming concepts applied to hardware design.

With a practical focus, the training addresses modern functional verification methodologies such as constrained random verification, code coverage and functional coverage, as well as the Universal Verification Methodology (UVM). Participants will work with complete verification environments, including testbench design and transaction modeling techniques, to validate digital systems of medium complexity.

This microcredential is aimed at students and professionals in the field of electronic engineering, computer science and digital systems who want to acquire practical skills aligned with the current needs of the industry.