Research Support Investigator
Nuria Elizondo Cereza
Student of the Degree in Data Science and Engineering
Development of an Interactive Graphical Tool for Optimization and Editing of Floorplanning in Chip Design
Development of an Interactive Graphical Tool for Optimization and Editing of Floorplanning in Chip Design
Description
This project focuses on the creation of an advanced graphical tool for chip designers that allows interactive editing of floorplans by modifying the shape and position of modules. The tool facilitates the introduction of design constraints, such as fixed locations or specific sizes, to optimize the physical architecture of the chip. A fundamental aspect is its integration with optimization tools developed by its colleagues, so that the graphical interface complements and improves the initial automated proposals. The main goal is to make the design process more interactive and collaborative, combining human knowledge with algorithmic automation.Background
Nuria is a second-year student in the Degree in Data Science and Engineering at the Polytechnic University of Catalonia (UPC). Her academic profile combines analytical skills in data science with an interest in practical applications in the field of hardware design and user interfaces.Motivation
His participation in this research stems from his desire to learn how to build complex graphical interfaces and to explore the field of chip design, a sector he considers to be of great relevance and current interest. This project has offered him the opportunity to discover a new technological area and apply his programming skills in an industrial R&D environment.
Host Organization
Supervisors
Jordi Cortadella
UPC supervisor
The content of this website reflects only the views of the Catedra Chip Chair UPC project.
