High Predictability Global Routing during Floorplanning of Complex Chips

Description

This project addresses the challenge of premature global routing in very large scale integrated circuit (VLSI) design. The goal is to improve the predictability and performance of routing immediately after the floorplanning stage and before final placement, using a mathematical optimization model based on multi-commodity flow and Linear Programming (LP). This methodology allows to minimize the total wiring length, the use of vias and the module crossings, while respecting the physical constraints of complex designs. The research integrates the theoretical rigor of Eindhoven University of Technology (TU/e) and the UPC with the practical validation of Qualcomm engineers, directly contributing to the development of state-of-the-art Electronic Design Automation (EDA) tools.

Background

Antoni graduated in Mathematics with a minor in Computer Science from the University of Barcelona (UB). He subsequently completed a Master's degree in Data Science and Artificial Intelligence through the EIT Digital program, with stays at the Eindhoven University of Technology (TU/e) and the University of Turku (UTU). His academic background stands out for its solid experience in optimization, graph modeling and algorithm design. Professionally, he has consolidated this knowledge by collaborating with Qualcomm and the UPC Chip Chair, where he has acquired practical experience in VLSI design flows and EDA tools.

Motivation

His research is driven by the exponential growth in chip complexity, which requires algorithms capable of anticipating routing problems early in the design flow. Antoni seeks to transform mathematical theory into practical engineering methods that improve design quality and reduce computational cost, generating real industrial impact. He is particularly motivated by the development of more reliable and sustainable EDA tools that accelerate innovation in the semiconductor industry.