Development of Mathematical and Heuristic Optimization Tools for Chip Floorplanning

Description

This project has as its primary objective the development of high-quality tools for the floorplanning stage in the context of chip design, in close collaboration with Qualcomm. The core of the research focuses on the application of mathematical and heuristic optimization techniques to generate highly efficient physical layouts (floorplans). This approach allows to address the complexity of modern integrated circuits from an algorithmic perspective, seeking solutions that balance the various technical requirements of the chip architecture.

Background

Guillem is a Data Science and Engineering undergraduate student at the Polytechnic University of Catalonia (UPC). His interdisciplinary training allows him to apply data engineering principles and quantitative methods to complex microelectronic design problems, facilitating the creation of new tools for electronic design automation (EDA).

Motivation

His motivation stems from the critical importance of floorplanning in the performance and efficiency of semiconductor devices. Guillem is driven by the opportunity to use his academic knowledge to optimize physical designs, with the aim of making chips more powerful and energy-efficient. The possibility of applying data engineering to solve real-world hardware challenges is the driving force behind his research within the Chip Chair.