Development of Mathematical and Heuristic Optimization Tools for Chip Floorplanning

Development of Mathematical and Heuristic Optimization Tools for Chip Floorplanning

Description

This project has as its primary objective the development of high-quality tools for the floorplanning stage in the context of chip design, in close collaboration with Qualcomm. The core of the research focuses on the application of mathematical and heuristic optimization techniques to generate highly efficient physical layouts (floorplans). This approach allows to address the complexity of modern integrated circuits from an algorithmic perspective, seeking solutions that balance the various technical requirements of the chip architecture.

Background

Guillem is a Data Science and Engineering undergraduate student at the Polytechnic University of Catalonia (UPC). His interdisciplinary training allows him to apply data engineering principles and quantitative methods to complex microelectronic design problems, facilitating the creation of new tools for electronic design automation (EDA).

Motivation

His motivation stems from the critical importance of floorplanning in the performance and efficiency of semiconductor devices. Guillem is driven by the opportunity to use his academic knowledge to optimize physical designs, with the aim of making chips more powerful and energy-efficient. The possibility of applying data engineering to solve real-world hardware challenges is the driving force behind his research within the Chip Chair.

Research Support Investigator

Guillem Pastor Rué

Guillem Pastor Rué

Data Science and Engineering undergraduate student

Host Organization

Supervisors

Jordi Cortadella

Jordi Cortadella

UPC supervisor

The content of this website reflects only the views of the Catedra Chip Chair UPC project.

Optimizing distributed AI workload training on multinode computing systems

Sergi Tomàs Martínez

Sergi Tomàs Martínez

Research Support Investigator

Simulation-Based Recommendation Framework for Scalable Training of Distributed AI

Tomàs Gadea Alcaide

Tomàs Gadea Alcaide

Research Support Investigator

Hierarchical floorplanning optimization algorithms for System-on-Chip architectures

Bernat Ibañez

Bernat Ibañez

Research Support Investigator

High Predictability Global Routing during Floorplanning of Complex Chips

Antoni Pech Alberich

Antoni Pech Alberich

Research Support Investigator

Mathematical Optimization Techniques for Hierarchical Floorplanning of Complex Chips

Yilihamujiang Yimamu

Yilihamujiang Yimamu

Predoctoral Researcher

Optimization of Training Distributed AI Workloads on Multi-node Computing Systems.

Xavier Querol Bassols

Xavier Querol Bassols

Research Support Investigator

Development of an Interactive Graphical Tool for Optimization and Editing of Floorplanning in Chip Design

Nuria Elizondo Cereza

Nuria Elizondo Cereza

Research Support Investigator

Optimization of Training Distributed AI Workloads on Multi-node Computing Systems

Mohammad Nasser

Mohammad Nasser

Predoctoral Researcher

This site is registered on wpml.org as a development site. Switch to a production site key to remove this banner.