Hierarchical floorplanning optimization algorithms for System-on-Chip architectures

Description

Moore's Law states that the number of transistors in an integrated circuit doubles approximately every two years. The problem of how to arrange these transistors to meet power and area constraints is known as chip floorplanning. The research conducted in collaboration with Qualcomm consisted of exploring new algorithms for this process, using techniques based on SAT solvers and heuristics to improve the performance of mathematical optimization. These techniques were subsequently applied to real Qualcomm System-on-Chip (SoC) architectures.

Background

Bernat is currently pursuing a double degree in Mathematics and Computer Engineering at the Polytechnic University of Catalonia (2021–2026), where he has obtained excellent grades with honors in core subjects of architecture and systems. His academic excellence is supported by scholarships from the Center for Interdisciplinary Higher Education (CFIS) and Semidynamics. As part of his international and research profile, he is carrying out his Final Degree Project at MIT CSAIL (2025–2026), under the supervision of Professor Daniel Sánchez, focused on hardware accelerators for distributed computing.

Motivation

On his path to becoming a hardware engineer, he realized that the future of computing depends on how the physical limitations of chip design are managed. Floorplanning sits at the critical intersection of electrical engineering and mathematics, allowing him to leverage his academic background to address real-world bottlenecks in hardware scaling. His primary motivation is to make an impact: through research into more energy-efficient chip design, he wants to contribute to enabling future advances in artificial intelligence and science.