Mathematical Optimization Techniques for Hierarchical Floorplanning of Complex Chips

Mathematical Optimization Techniques for Hierarchical Floorplanning of Complex Chips

Description

This project develops new mathematical optimization techniques for hierarchical floorplanning in cutting-edge chip design. The main goal is to efficiently partition a complex chip into manageable blocks and optimize their physical layout to minimize total area, wiring length, and power consumption. The research focuses on formulating and solving non-convex problems to address the NP-hard nature of this challenge. In collaboration with Qualcomm, the project validates the algorithms with real industrial designs, with the goal of significantly reducing design cycle time and improving the final device performance.

Background

Yilihamujiang holds a Bachelor's and Master's degree in Mathematics. He is currently a PhD candidate in Computer Science at UPC, where his research focuses on inverse problems in mathematical physics, regularization methods, partial differential equation theory (PDE) and numerical computing. He has international experience as a research assistant at City University of Hong Kong and has applied his technical skills in industry, working on privacy computing, federated learning and software development at Oracle OAEC Talent Industry.

Motivation

His intellectual trajectory is driven by a fundamental desire to connect abstract mathematical theory with tangible real-world challenges. He believes that this research, validated through industrial collaboration, has the potential to reduce development costs and boost innovation across the technology sector, from artificial intelligence to mobile computing. This synergy between deep mathematical knowledge and transformative industrial application is at the core of his research ambition.

Predoctoral Researcher

Yilihamujiang Yimamu

Yilihamujiang Yimamu

Degree and Master's degree in Mathematics, currently a PhD candidate.

Host Organization

Supervisors

Jordi Cortadella

Jordi Cortadella

UPC Supervisor

The content of this website reflects only the views of the Catedra Chip Chair UPC project.

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Sergi Tomàs Martínez

Research Support Investigator

Simulation-Based Recommendation Framework for Scalable Training of Distributed AI

Tomàs Gadea Alcaide

Tomàs Gadea Alcaide

Research Support Investigator

Hierarchical floorplanning optimization algorithms for System-on-Chip architectures

Bernat Ibañez

Bernat Ibañez

Research Support Investigator

High Predictability Global Routing during Floorplanning of Complex Chips

Antoni Pech Alberich

Antoni Pech Alberich

Research Support Investigator

Optimization of Training Distributed AI Workloads on Multi-node Computing Systems.

Xavier Querol Bassols

Xavier Querol Bassols

Research Support Investigator

Development of an Interactive Graphical Tool for Optimization and Editing of Floorplanning in Chip Design

Nuria Elizondo Cereza

Nuria Elizondo Cereza

Research Support Investigator

Optimization of Training Distributed AI Workloads on Multi-node Computing Systems

Mohammad Nasser

Mohammad Nasser

Predoctoral Researcher

Development of Mathematical and Heuristic Optimization Tools for Chip Floorplanning

Guillem Pastor Rué

Guillem Pastor Rué

Research Support Investigator

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