Software development for random generation of chip designs

Software development for random generation of chip designs

Description

The project focuses on developing software that allows the generation of chip floorplans in a random manner. This includes a random positioning of the chip components and their connections and some characteristics are determined by a series of parameters chosen by the user using this tool. The objective is twofold: to be able to use these designs to test and evaluate floorplanning optimization programs; and to generate sets of varied floorplans to train artificial intelligence models in this task, reducing the risk of overfitting thanks to the controlled diversity of the randomly generated examples.

Background

I am a student of the Degree in Data Science and Engineering at the Polytechnic University of Catalonia (UPC). My training combines a solid foundation in mathematics and programming with a marked interest in data analysis and algorithmic design, which I apply in projects related to software development and the automation of engineering processes.

Motivation

This project has been an opportunity to delve into the realm of applied software development and to discover the world of chip design. It has allowed me to test my programming skills in a real-world context and discover how my training can bring value to technological fields that I had not initially considered exploring.

Research Support Investigator

Emma Tarancón Estrada

Emma Tarancón Estrada

Student of the Degree in Data Science and Engineering / Research Support Researcher

Host Organization

Supervisors

Jordi Cortadella

Jordi Cortadella

Supervisor UPC

The content of this website reflects only the views of the Catedra Chip Chair UPC project.

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