Development of an Adaptive Neuromorphic Processor with Sensor Integration and Scalable SNN Architecture

Description

This project focuses on the expansion of an internally developed Spurious Neural Network (SNN) hardware architecture to reduce power consumption and enable real-time evolvable systems that directly interact with external sensors. The key goal is to improve scalability, allowing multiple complex networks to operate in parallel and interconnect to implement biologically accurate models that emulate functional regions of the brain. The work combines the design of efficient ASICs with real-time neuromorphic computing, advancing both bioinspired computing and experimental research applications.

Background

Arnau holds a bachelor's and master's degree in Electronic Engineering from the UPC. His master's thesis focused on the design and implementation of an on-chip SNN emulator using 28 nm CMOS technology. This academic career has provided him with solid experience in ASIC architectures for neural processing, efficient hardware-based SNN modeling, and full-custom digital design methodologies. Since 2024, he has been working on his PhD in the Intelligent Sensors and Integrated Systems (IS2) research group at the UPC, where he contributes to the design, optimization, and verification of digital SNN hardware.

Motivation

His research stems from a fascination with the intersection of electronics and neuroscience. Arnau is motivated by the applications of biomimetic systems that facilitate the study of real neurons and neurological pathologies, as well as by the development of closed-loop systems that allow direct interaction between biological and digital neurons. He is motivated by the challenge of working in a constantly evolving field that drives him to explore new ideas to improve the efficiency of bioinspired models.