Irina Selin Lorenzo
Master's and Bachelor's Degree in Electronic Engineering
Goleta-UPC: Implementing a 65nm RTL-to-GDSII SoC design flow
Goleta-UPC: Implementing a 65nm RTL-to-GDSII SoC design flow
Description
Design and development of a complete testing and programming ecosystem for the Goleta-UPC (Caravel-based SoC). This includes the complete hardware design of a multi-voltage PCB carrier board and the implementation of high-speed firmware flashing interfaces to ensure optimal SoC validation and accurate performance characterization.Background
Irina is a Master's student in Electronic Engineering at the UPC and graduated in Industrial and Automatic Electronic Engineering. She currently works as a laboratory technician in the IS2 research group (Smart Sensors and Integrated Systems), where she participates in experimental support tasks, device characterization and development of electronic systems applied in the field of smart sensors and integrated technologies. Her career combines a solid background in industrial electronics with practical experience in laboratory environments and applied research.
Motivation
His passion for electronic engineering is driven by the challenge of bridging the gap between theoretical microelectronic design and functional hardware implementation. His incorporation into the Cátedra Chip project allows him to apply his expertise in SoC testing and PCB design within a cutting-edge RISC-V ecosystem. What motivates him most is the opportunity to contribute to the technological sovereignty of the European semiconductor industry. By developing the test platform for Goleta-UPC, he contributes to ensuring the reliability and accessibility of open source hardware. His goal is to advance the field of embedded systems while preparing for a career in academic research.
Host Organization
Supervisors
Francesc Moll Echeto
Jordi Cosp Vilella
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