Automation Methodologies for the Systematic Design of Integrated Analog Blocks

Automation Methodologies for the Systematic Design of Integrated Analog Blocks

Description

This project focuses on defining and creating reference design topologies for several critical analog blocks, such as OTAs (Operational Transconductance Amplifiers) and LDOs (Low Dropout Regulators). The goal is to implement a systematic design flow where these blocks are optimized based on specific input constraints and rigorously validated through simulations. This methodology seeks to standardize and automate analog design to advance towards more efficient systems within microelectronics.

Background

Victor is a Master's student in Electronic Engineering at the UPC, specializing in Microelectronic Design. He holds a double degree in Mechanical Engineering and Industrial and Automatic Electronic Engineering from the same university. In his professional career, he has worked at Teknics Engineering in the assembly and programming of PLCs for the automotive and cosmetics industry, and later in the IS2 (Intelligent Sensors and Integrated Systems) research group at the UPC, where he developed and tested PCBs for the validation of integrated circuits.

Motivation

His research is driven by the challenge of combining analog circuit design with systematic design automation. Victor seeks to transcend time-consuming design practices towards specification-based workflows that improve efficiency, reproducibility, and final chip quality. His central goal is the development of reusable tools and methodologies that accelerate analog and mixed-signal design, thereby facilitating sustained technological innovation.

Research Support Investigator

Víctor Torres Collantes

Víctor Torres Collantes

Double Degree in Mechanical Engineering and Industrial and Automatic Electronic Engineering and Master's Degree in Electronic Engineering

Host Organization

Supervisors

Jordi Madrenas

Jordi Madrenas

UPC Supervisor

The content of this website reflects only the views of the Catedra Chip Chair UPC project.

Caravel UPC

Irina Selin Lorenzo

Irina Selin Lorenzo

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