Elastic Vector Architecture RISC-V

Elastic Vector Architecture RISC-V

Description

The research focuses on improving the performance and energy efficiency of GPU hardware. The project specifically addresses address translation and memory management optimization in systems with multiple interconnected GPUs.

Background

Hari holds a degree in Electrical Engineering from IIT Bombay , where he collaborated in the Computer Architecture Laboratory (CADSL). Professionally, he has worked at Micron Technology as a NAND device test engineer. He holds a Master's degree in High Performance Computing (HPC) from the UPC , with a thesis carried out in the ARCO group on the optimization of GPU architecture for energy efficiency.

Motivation

He is driven by the challenge of solving complex problems with great social and industrial impact. Given that GPUs are fundamental to AI , machine learning, and medical imaging , Hari seeks to improve this hardware to benefit all the industries that depend on it.

Research Support Investigator

Vasabhaktula Lokananda Hari Babu

Vasabhaktula Lokananda Hari Babu

Degree in Electrical Engineering and Master in High Performance Computing

Host Organization

The content of this website reflects only the views of the Catedra Chip Chair UPC project.

Caravel UPC

Irina Selin Lorenzo

Irina Selin Lorenzo

Agent de recerca

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Dídac Llobet Muñoz

Dídac Llobet Muñoz

Research Support Investigator

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Víctor Torres Collantes

Víctor Torres Collantes

Research Support Investigator

Development of an Adaptive Neuromorphic Processor with Sensor Integration and Scalable SNN Architecture

Arnau Larre Alos

Arnau Larre Alos

Research Support Investigator

Simulation and Automated Evaluation of Digital Circuits

Miquel Torner Viñals

Miquel Torner Viñals

Research Support Investigator

Implementing a 65nm RTL-to-GDSII SoC design flow

A.Joshua Castro Sisniegas

A.Joshua Castro Sisniegas

Research Support Investigator

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