Simulation and Automated Evaluation of Digital Circuits

Description

This project aims to optimize hands-on learning of digital circuit design through an integrated platform that combines simulation and automated assessment. Using the Jutge.org infrastructure, the system connects tools such as Digital and CircuitVerse to allow students to design and simulate circuits in an intuitive graphical environment. The key innovation lies in the automated verification using Verilog, which provides consistent and accurate assessment, reducing the burden of manual correction and encouraging active learning in electronic and computer engineering.

Background

Miquel graduated in Computer Engineering from the UPC (2020-2025) . He has a markedly international academic career, with exchange stays at Aalto University (Finland), Grenoble INP–UGA (France) and Beijing Institute of Technology (China). In addition, he has worked as a professor of Aula Lliure for the subject "Programming 1" at the UPC, an experience that has allowed him to directly understand the pedagogical needs in the field of computing.