Implementing a 65nm RTL-to-GDSII SoC design flow

Description

The Caravel UPC project is an advanced educational initiative that offers a comprehensive hands-on experience in the design of Systems on a Chip (SoC) using the open source Caravel template. The goal is for the student to cover all critical stages of the silicon life cycle: from the development of intellectual property (IP) in RTL to the implementation of the physical design using industry standard EDA tools. Using an industrial 65nm technology node, the project allows to address real manufacturing and post-manufacturing verification challenges, preparing engineers for the current demands of the semiconductor industry.

Background

Aarón Joshua is a Master's student in Electronic Engineering at the UPC, where he also obtained his Bachelor's degree in Telecommunications Technology and Services Engineering, specializing in Electronic Systems. His academic background is focused on the design of complex systems and microelectronics, providing him with the necessary foundation to manage high-level hardware design flows.

Motivation

His main motivation is to master the full RTL-to-GDSII design flow, seeking to demystify the chip creation process beyond theoretical simulation. Aaron Joshua seeks to confront the real-world complexities of physical design, such as timing closure, power planning, and layout verification. With this project, he aims to transform academic knowledge into technical skills directly applicable to the semiconductor engineering industry.