Caravel UPC

Description

Design and development of a complete testing and programming ecosystem for the Goleta-UPC (Caravel-based SoC). This includes the complete hardware design of a multi-voltage PCB carrier board and the implementation of high-speed firmware flashing interfaces to ensure seamless SoC validation and performance characterization.

Background

Master's student in Electronic Engineering at the UPC. Degree in Industrial Electronics and Automation Engineering. Laboratory technician at the IS2 Group (Intelligent Sensors and Integrated Systems).

Motivation

My passion for electronic engineering is driven by the challenge of bridging the gap between theoretical microelectronic design and functional hardware implementation. Joining the Catedra Chip project allows me to apply my expertise in SoC testing and PCB design to a cutting-edge RISC-V ecosystem. What motivates me most is the opportunity to contribute to the technological sovereignty of the European semiconductor industry. By developing the test platform for Goleta-UPC, I am helping to ensure the reliability and accessibility of open source hardware. My goal is to advance the field of embedded systems while preparing for a career in academic research.